Since 2026, the global semiconductor market has continued to heat up driven by the AI wave. After a steady recovery in 2025, AI chip demand has exploded this year, especially the thirst for computing power from large language models (LLMs) and generative AI applications, directly driving strong demand for advanced processes and packaging. Among them, TSMC's CoWoS (Chip-on-Wafer-on-Substrate) packaging capacity remains critically tight, becoming a key bottleneck in the AI chip supply chain.
CoWoS Capacity Tight, TSMC Accelerates Expansion
According to industry sources, TSMC's CoWoS monthly capacity reached about 45,000 wafers by Q2 2026, nearly double that of the same period last year, but still far from meeting order demand from NVIDIA, AMD, Broadcom, and others. The industry estimates that 2026 full-year AI chip demand for CoWoS will exceed 60,000 wafers per month, with a gap of over 30%. To address this, TSMC has announced simultaneous expansion of advanced packaging facilities in Hsinchu, Central Taiwan, and Southern Taiwan Science Parks, aiming to push CoWoS monthly capacity above 80,000 wafers by 2027. Meanwhile, TSMC has begun collaborating with packaging/testing giants ASE and Amkor for partial process outsourcing.
NVIDIA and AMD Vie for Advanced Packaging Capacity
Currently, NVIDIA's Blackwell architecture GPU and its successor B200 both use CoWoS packaging, with each chip requiring about one 12-inch wafer-grade interposer. With over 80% market share in AI accelerators, NVIDIA's CoWoS capacity consumption is the most significant. Meanwhile, AMD's MI400 series accelerators have also turned to more advanced 3D packaging architecture, likewise relying on TSMC's CoWoS-L technology. The fierce competition between the two giants has tightened packaging capacity further, extending lead times for some orders to over six months.
Packaging/Testing Supply Chain Benefits, Revenues Hit Highs
The CoWoS capacity crunch has not only driven up packaging/testing prices but also boosted the entire supply chain's performance. ASE, a leading packaging/testing company, saw its H1 2026 revenue grow 25% YoY, with advanced packaging contributing over 40% of the growth. Other players like SPIL and KYEC also benefited from increased interposer and testing demand. On the material side, substrate suppliers such as Ibiden (Japan) and Kinsus (Taiwan) are running at full capacity and planning new production lines to meet demand for the next two years.
Supply Bottleneck Spurs Tech Change and New Opportunities
To ease CoWoS capacity pressure, the industry is actively exploring alternatives. Intel's EMIB packaging technology and Samsung's I-Cube/X-Cube solutions are gaining some customer favor, but their ecosystems are less mature than TSMC's. Meanwhile, the proliferation of chiplet designs and the UCIe standard is leading more chip design companies to consider multi-die heterogeneous integration, reducing reliance on a single advanced packaging process. In addition, glass substrate technology is seen as a potential breakthrough for current packaging bottlenecks; several substrate vendors have invested in R&D, with initial products expected by 2027.
Investor Focus and Risk Warnings
For semiconductor investors, advanced packaging has become a key track second only to advanced process technology. Leaders like TSMC, ASE, and NVIDIA will continue to benefit, but the market should also be wary of oversupply risk after excessive capacity expansion. Geopolitical factors, such as US export restrictions on semiconductor equipment to China, could affect the supply of packaging/testing equipment and delay expansion. Overall, AI-driven advanced packaging demand will remain strong for the next 2-3 years, and suppliers with core technologies are likely to see superior returns.
Conclusion
The main theme of the semiconductor market in 2026 is undoubtedly the deep integration of AI and advanced packaging. The CoWoS capacity crunch is both a challenge and an opportunity, driving not only the upgrade and expansion of the packaging/testing industry but also the diversification of technology paths. Investors should closely monitor vendors' expansion progress, customer order changes, and new technology breakthroughs to seize opportunities in the rapidly changing semiconductor market.
